Intel Foundry Direct Connect 2025: Perspectives of a low level software developer

 

I love seeing the Boston Dynamics Spot cameo in unexpected places. Over here, Chip is used for QC purposes.

I recently attended a livestream event from Intel Foundry (think Intel's hardware R&D + Manufacturing wing which partners with other companies and manufactures processors), and as someone who spends a good chunk of time buried in low-level systems – delving into OSes and how compilers really work – this was pretty fascinating stuff. Seeing how the foundational layer of computing, the actual silicon manufacturing, is evolving felt directly relevant to the software I tinker with: even though I know very little in this hardware domain. 

A big part of the discussion was their process technology roadmap. From my perspective, understanding this is key because it dictates the fundamental capabilities that operating systems and compilers have to work with. This roadmap is basically their plan for creating the next generations of silicon chips with smaller, more efficient components. They gave updates on their Intel 18A process – that's the name for a specific, very advanced manufacturing node they've been working on, and it's now in something called "risk production," which means they're getting pretty close to being ready for high-volume manufacturing. They also introduced the next step after that, which they're calling Intel 14A. One cool detail about 14A is that it will use PowerDirect contact power delivery, a new way to get power to the tiny parts of the chip more effectively. This kind of innovation at the transistor level has ripple effects up the software stack, influencing power management features in the OS. They also touched on variations of their processes, like 18A-P and 18A-PT, and their ongoing work on nodes like the 12nm and 16nm generations (through this paragraph, A=Armstrong and nm = nanometer, defining how close transistors are stacked to each other, thus defining throughput and raw compute).

They also spent a good amount of time on advanced packaging technologies. This is super interesting because it's all about how they connect and stack different pieces of chips together in a single package, going way beyond just sticking one chip on a board. From an OS perspective, how chips are packaged affects how the OS manages resources like memory and inter-chip communication. They talked about EMIB-T, which is a type of 2.5D packaging that links chips side-by-side within a package, and the Foveros technology, which is their method for stacking chips on top of each other in 3D integration. They introduced new versions, Foveros-R and Foveros-B, offering more options for how these stacked chips are connected (interconnects). These packaging tricks are going to be essential for building the powerful chips needed for HPC and AI workloads. Understanding these hardware layouts is crucial for optimizing software performance. It looks like Panther Lake, which was mentioned alongside the 18A node as a focus for 2025, might be one of the first products to really leverage these advancements, which is exciting for low-level optimization opportunities.

It felt encouraging to see Intel talk openly about their journey and how they're refocusing heavily on foundational R&D. For someone like me, who's spent time with OS internals and even a bit of BSD kernel work, seeing a major hardware vendor emphasize the fundamentals is a good sign. 

As I was listening to all this, it really made me think about my own Honors Thesis. I spent a lot of time digging into the performance differences between programming languages like C++ and Rust at a really low level, looking at the assembly code on x86 processors. My research specifically looked at how compiler behavior and the structure of low-level code impact real-world performance on these widely used architectures. So, to hear Intel talking about similar ideas from the hardware side pushing for platforms that are not just fast, but also efficient and secure felt incredibly validating and showed a clear connection between the silicon and the software layers I focus on. Intel's emphasis on power efficiency and making performance growth sustainable resonated with me quite a bit. My thesis work definitely highlighted that squeezing more performance out of computers while using less energy requires effort on both the hardware (what Intel is doing with their process and packaging) and the software/language side (how OSes manage resources, especially in HPC and AI servers). Seeing them focus on that alignment was pretty exciting.

Up until 2020, most chip manufacturers were largely considering advancements in raw performance, without much regard to the power consumption. Moving in a world where more human-computer interactions are getting relegated to cloud compute, web apps, high performance AI compute, and safeguarding a lot of sensitive data: putting raw performance as the only metric can prove to be environmentally harmful. Apple Silicon was the first processor which put the ratio of power to performance at the helm: super powerful yet sips on electricity (in fact, the new Macs can run LLMs on-device locally while charging from a phone charger). x86 chips up until this point were largely more powerful than ARM (which is what Apple Silicon is based on), but used a lot of power.

Intel's Lunar Lake processors were among the first which bought a good power to performance ratio on the table, and Panther Lake was mentioned to be the next iteration of this chipset ready to launch later in 2025. My current laptop is a Samsung Galaxy Book4, with a Meteor Lake processor: one iteration before Lunar Lake. As someone who also has a Core i7 laptop, the difference in heat dissipation, power consumption, battery life, and performance are all evident: and positively so. It's especially amazing to see Intel bringing this level of efficiency to x86.

However, a rather unexpected collaboration announced at this event was that with MediaTek: the mobile chip manufacturer. It will be interesting to see MediaTek manufacture the next generation of their ARM chips using these new Intel manufacturing technologies, and if that upstreams into some Intel ARM chips later on (speculation).

(While all of this is happening, I hope/pray for RISC-V to gain traction)

For a low-level systems person, understanding these hardware advancements is key to writing better software that can actually take advantage of them. It reinforced my interest in how everything from the lowest levels of code, through the OS and compilers, all the way down to the physical chip impacts computing. I'm looking forward to seeing how these foundry developments play out and shape future technology!

All pictures used in this post are courtesy of Intel, released either during their event or their press release.

Intel's newsroom release: link